Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as "die". The "die" are also commonly referred to as "chips" and comprise the finished circuitry components of, for example, processors and memory circuits. Common types of memory circuitry includes DRAM and SRAM chips.
After a semiconductor wafer has been fabricated, not all chips provided on the wafer prove operable, resulting in a less than 100% yield. Accordingly, individual die must be tested for functionality. The typical test procedure for DRAM or SRAM circuitry is to first etch the upper protective passivation layer to expose desired bonding pads on the individual die. Thereafter, the wafer is subjected to test probing whereby the individual die are tested for satisfactory operation. Inoperable die are typically identified by an ink mark. After testing, the wafer is severed between the individual die, and the operable, non-marked die are collected.
The "operable" individual die are then assembled in final packages of either ceramic or plastic. After packaging, the die are loaded into burn-in boards which comprise printed circuit boards having individual sockets connected in parallel. The burn-in boards are then put into a burn-in oven and the parts are subjected to burn-in testing. During burn-in, the die are operated for a period of time at different temperature cycles, including high temperatures. The die are stressed to accelerate their lives in an effort to determine when the die are likely to fail. Manufacturers predict early failures, known as "infant mortalities", to occur within a predetermined period of time of the burn-in cycle. Burn-in testing is conducted for a period of time sufficient to reveal infant mortalities. For example, if infant mortalities are expected to occur within 48 hours of burn-in testing, the burn-in test can be completed within this time period. In this manner, semiconductor wafer manufacturers can effectively test the quality of their chips in a reasonable time frame prior to shipping these chips to the consumer.
According to the above burn-in testing procedures, the die are subjected to a test before severing, and a second test after severing and packaging of the individual die. Therefore, two separate tests are required.
U.S. Pat. No. 5,047,711 to Smith et al. discloses a technique whereby individual circuits are subjected to burn-in testing while still constituting a part of a wafer which has not yet been severed. It would be desirable to improve upon these and other techniques for fabricating wafers and testing individual die prior to their severing from the semiconductor wafer.